|
3rd
Workshop
on
Dependable and
Secure Nanocomputing
Monday June 29, 2009 — Estoril,
Lisbon, Portugal
|
Organizers: |
•
Jean Arlat, LAAS-CNRS, Université de
Toulouse, France
• Cristian
Constantinescu, AMD, Fort Collins, CO, USA
• Ravishankar
K. Iyer, UIUC, Urbana, USA
• Johan Karlsson, Chalmers University of Technology, Göteborg,
Sweden
• Michael
Nicolaïdis, TIMA, Université de Grenoble, France |
Schedule
|
Contributions |
Slides |
08:30-10:00
SESSION
1
Opening
and
Invited Talks
(See
Flyer) |
Moderator:
Jean Arlat |
|
Introduction
to the Workshop
Jean Arlat, Cristian Constantinescu,
Ravishankar K. Iyer, Johan Karlsson, Michael Nicolaïdis |
 0.5Mb |
Dependable
Design in Nanoscale CMOS Technologies: Challenges and Solutions
Vikas Chandra, ARM R&D, San Jose,
CA, USA
|
2.1Mb |
Trading
Off Dependability and Cost for Nanoscale High Performance Microprocessors:
The Clock Distribution Problem
Cecilia Metra, Università di Bologna, Italy |
3.6Mb |
10:00-10:30 |
Coffee
Break |
|
10:30-12:00
SESSION
2
Reliability
Issues
and Assessment
|
Moderator: Johan
Karlsson |
|
Scaling
Effects on Neutron-Induced Soft Error in SRAMs Down to 22nm Process
Eishi Ibe, Hitoshi Taniguchi, Yasuo Yahagi, Ken-ichi Shimbo,
Tadanobu Toba; Hitachi Ltd, Yokohama, Japan |
0.6Mb |
On
CMOS Circuit Reliability from MOSFETs and Input Vectors
Valeriu Beiu (1,2), Walid Ibrahim(1,3); (1) UAE University, Al-Ain,
UAE; (2) University of Ulster, Londonderry, UK; (3) Carleton University,
Ottawa, Canada
|
4.4Mb |
Impact
of Manufacturing Defects on Carbon Nanotube Logic Circuits
Daniel Gil, David
de Andrés, Juan-Carlos Ruiz, Pedro Gil; Universidad
Politécnica de Valencia, Spain |
0.8Mb |
Enhanced
Fault Coverage Analysis Using ABVFI
Scott Bingham, John Lach; University of Virginia, Charlottesville,
USA |
5.8Mb |
12:30-13:30 |
Lunch |
|
13:30-15:00
SESSION
3
Resilience
Enhancement Techniques
|
Moderator:
Michael Nicolaïdis
|
|
Achieving
Degradation Tolerance in a Hardware Accelerator with Parallel Functional
Units
Tomohiro Yoneda, National Institute of Informatics, Tokyo; Masashi
Imai, University of Tokyo;
Hiroshi Saito, University of Aizu; Atsushi
Matsumoto, Tohoku University, Sendai; Japan |
0.7Mb |
|
Software Mechanisms for Tolerating Soft Errors in an Automotive
Brake-controller
Daniel Skarin, Johan Karlsson; Chalmers University of Technology,
Göteborg, Sweden |
0.2Mb |
Power
Efficient Redundant Execution for Chip Multiprocessors
Pramod Subramanyan(1), Virendra Singh(1), Kewal Saluja(2), Erik
Larsson(3); (1) Indian Institute of Science, Bangalore, India; (2)
University of Wisconsin-Madison, USA; (3) Linköping University,
Sweden |
0.3Mb |
On
the Stability and Robustness of Non-Synchronous Circuits with Timing
Loops
Matthias Függer, Gottfried Fuchs, Ulrich Schmid, Andreas
Steininger;
Vienna University of Technology, Austria |
0.4Mb |
15:00-15:30 |
Coffee
Break |
|
15:30-17:00
SESSION
4
Panel
and
Closing
|
Panel
“Scaling towards Nanometer Size Devices - Issues and Solutions”
Moderator: Cristian
Constantinescu
|
|
Panelists:
|
|
• Jacob
A. Abraham, University of Texas, Austin, USA
Dependable Systems with Nanometer
Scale Technologies: What is Different?
|
0.4Mb |
• Valeriu
Beiu, UAE University, Al-Ain, UAE and University of Ulster, Londonderry,
UK
Why Brain-inspired Architectures Could
Save the Day?
|
6Mb |
• Helia
Naeimi, Intel Corporation, Santa Clara, CA, USA
Cross-Layer Resiliency for Nano-scale Technology
|
0.9Mb |
• Arun
Somani, Iowa State University, Ames, USA
Aggressive and Adaptive Mitigation
Techniques may be Key to the Solution
|
0.5Mb |
• Seongmoon
Wang, NEC Laboratories America, Princeton, NJ, USA
Now Silicon is Cheap, but Testing is Expensive
|
3.2Mb |
| Workshop
Wrap-Up |
|
17:00 |
Adjourn |
|
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