Workshop on Dependable and Secure Nanocomputing

LogoDSN07 Thursday June 28, 2007, Edinburgh, Scotland, UK
Organizers:  Jean Arlat, LAAS-CNRS, Toulouse, France
                      Ravishankar K. Iyer, UIUC, Urbana-Champaign, USA
                      Michael Nicolaïdis, TIMA and iROC, Grenoble, France

Program and Content

Schedule  Contributions (Title links to the .pdf version of written material; Presenter)  Slides
Session 1


Track 6D
Introduction to the Workshop
Jean Arlat, Ravishankar K. Iyer and Michael Nicolaïdis
Emerging Accidental Faults and Malicious Threats
Moderator: Sudhakar M. Reddy, The University of Iowa, Iowa City, USA

Manufacturing Process Variations and Dependability - A Contrarian View
Janak H. Patel, University of Illinois at Urbana-Champaign, USA
pdf-icon 3Mb
Physically Secure Cryptographic Computations: From Micro to Nano Electronic Devices
Jean-Jacques Quisquater and François Xavier Standaert, Université Catholique de Louvain, Belgium
Coffee Break*
Session 2

11:00 - 13:00

Track 7D
From Transient Faults to Architectural Design Issues
Moderator: Lorena Anghel, TIMA, Grenoble, France
Environmental and Power-Induced Disturbance  
Impact of Intermittent Faults on Nanocomputing Devices
Cristian Constantinescu, Advanced Micro Devices Corp., Forts Collins, CO, USA
pdf-icon 0.6Mb
Judicious Choice of Waveform Parameters and Accurate Estimation of Critical Charge for Logic SER
Palkesh Jain, Texas Instruments, Bangalore, India and Vivian Zhu, Texas Instruments, Dallas, TX, USA
(presented by Rubin A. Parekhji)

pdf-icon 0.7Mb
Time Redundancy Processor with the Tolerance to Transient Faults Caused by Electromagnetic Waves
Makoto Kimura, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tokyo Metropolitan University, Japan
pdf-icon 0.3Mb
NBTI-Resilient Memory Cells with NAND Gates for Highly-Ported Structures
Jaume Abella, Xavier Vera, Osman Unsal, Antonio González, Intel Barcelona Research Center, Intel Labs - UPC, Barcelona, Spain
pdf-icon 0.1Mb
On-Line Testing and Chip-Level Configurability
A BIST Implementation Framework for Supporting Field Testability and Configurability in an Automotive SOC
Amit Dutta, Srinivasulu Alampally, Arun Kumar, Rubin A. Parekhji, Texas Instruments, Bangalore, India
pdf-icon 0.2Mb
Resilience through Self-Configuration in Future Massively Defective Nanochips
Piotr Zając, LAAS-CNRS and Université de Toulouse, France & Technical University of Lodz, Poland, Jacques Henri Collet, Jean Arlat and Yves Crouzet, LAAS-CNRS and Université de Toulouse, France
pdf-icon 1.4Mb
FPGA Hardware Implementation of Statically-derived Application-aware Error Detectors
Peter Klemperer, University of Illinois at Urbana-Champaign, USA, Shelley Chen, SAIC, Champaign, IL, USA, Karthik Pattabiraman, Zbigniew Kalbarczyk and Ravishankar K. Iyer, University of Illinois at Urbana-Champaign, USA
pdf-icon 28Kb
On-Line Self-Test of AES Hardware Implementations
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, LIRMM and Université de Montpellier, France
pdf-icon 3Mb
13:00 - 14:00 Lunch  
Session 3

14:00 - 15:30

Track 8D
Panel: Emerging Hardware Technologies and Related Dependability & Security Challenges
Moderator:   Johan Karlsson, Chalmers University of Technology, Göteborg, Sweden

pdf-icon 28Kb

Panelists:    Dependability in Conventional and Emerging Nanosystems
                     Jacob A. Abraham, University of Texas, Austin, TX, USA

pdf-icon 0.5Mb

                      Security Challenges for High Density Smart Cards
                     Helena Handschuh, Spansion EMEA, Levallois-Perret, France

pdf-icon 0.8Mb

                      Challenges in Nanocomputing for Dependability and Security
                     Takashi Nanya, University of Tokyo, Japan

pdf-icon 72Kb

                      Nanoelectronic Architectures: Reliable Computation on Defective Devices
                     Alex Orailoglu, University of California, San Diego, CA, USA

pdf-icon 1.4Mb
15:30 - 16:00 Coffee Break*  

 * Posters about contributions in the 11:00-13:00 session and about those listed below, are on display during the 10:30-11:00 and 15:30-16:00 coffee breaks

Coffee Break Sessions
Poster Only Presentations  
Identifying Fault Mechanisms and Models of Emerging Nanoelectronic Devices
Daniel Gil, David de Andrés, Juan-Carlos Ruiz, Pedro Gil, UPV, Valencia, Spain
On the Evaluation of Reliability of NanoFabric-based Architectures through Fault Simulation
Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda, Politecnico di Torino, Italy
An Application-Specific Framework for Detecting Transient Faults in Processors
Srivaths Ravi, Texas Instruments, Bangalore, India
CNES Developments for COTS-based Spacecraft Supercomputers
Michel Pignol, CNES, Toulouse, France
Design and Test Techniques for Better Defect Screening and Improved Reliability in Automotive Integrated Circuits
Udayakumar H., Rubin A. Parekhji, Texas Instruments, Bangalore, India