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3rd Workshop on Dependable and Secure NanocomputingIn conjunction with the 39th Annual IEEE/IFIP International Conference on Dependable Systems and Networks The Workshop is also linked to the 15th IEEE Int. Online Testing Symp. (IOLTS) that is taking place in Lisbon area on June 24-27, 2009 Highlights:
Invited Talks by Vikas Chandra, ARM R&D, US and Cecilia
Metra, Univ. of Bologna, IT |
Motivation and ThemeUnprecedented levels of information processing, novel architectural solutions and a new realm of applications promise to be reached thanks to the advances in semiconductor technologies for integrating extremely large numbers of transistors or processing elements into a chip. Towards this ends, two main tracks are being considered:
Due to the differences in relative advances and current industrial concerns attached to each track, this third edition of the Workshop will emphasize the top-down track for which it is widely recognized that such an evolution raises serious challenges both from the Dependability and Security viewpoints. Nevertheless, considerations attached to the emerging nanoscale technologies are also part of the scope of the Workshop. Indeed, such technologies are intrinsically exposed to a significant rate of residual defects and fault occurrence and — to some extent — reminds the early days of digital computers and relate to the seminal work then developed to improve their reliability. The long standing Moore’s Law-based trend in IC development is aiming at nanometric scale elementary devices. Such technologies are already impaired by significant variations affecting process parameters and thus become a nightmare to reliability engineers for reaching an acceptable manufacturing yield at viable cost. The dramatic reduction of digital devices is accompanied by a decrease in power supply and threshold levels which in turn results in lower noise immunity and greater exposure to particles. Moreover, additional instabilities may affect circuit parameters in operation, e.g., in CMOS devices negative bias temperature instability (NBTI) has a strong impact on threshold voltage over time. Examples of vulnerabilities and malicious threats related to hardware chips are information leakages attached to side channels attacks or differential fault analysis based on applying environmental disturbances or even fault injection. Device downsizing and increased chip complexity are commonly understood as positive factors in reducing hardware vulnerabilities with respect to security issues (especially for what concerns cryptochips or IC intellectual property). Nevertheless, one should not neglect the related problems attached to the observability and controllability facilities provided by scan-based testing devices incorporated into the chips. |
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Scope and ObjectivesThe Workshop is aimed at characterizing these impairments and threats as well as distinguishing the design approaches and operation control paradigms that have to be enforced and/or favored in order to keep achieving dependable and secure computing. Three main goals are identified for the Workshop:
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Participation, Submission and Selection ProcessThe Workshop is open to all researchers, system developers and users who are involved with or have an interest in dependability and security of hardware technologies. We are interested in submissions from both industry and academia on all topics related to dependable and secure nanocomputing. Potential topics of interest include, but are not limited to: failure modes and risk assessment, yield and mitigation techniques in nanoscale technologies, on-line adaptive and reconfigurable nanoarchitectures, design techniques for developing resilient nanosystems, fault-tolerant architectures specific to nanoscale circuits, scalable verification and testing methodologies, network on chip and communication protocols, etc. All prospective contributors should submit an extended abstract, work-in-progress report or position paper. Submissions must be original work with no substantial overlap with previously published papers or simultaneous submissions to a journal or conference with proceedings. The submissions should conform to the proceedings publication format (IEEE Conference style) and should not exceed six pages (including all text, references, appendices, and figures). They should explain the contribution to the field and the novelty of the work, making clear the current status of the work. Each submission should start with a title, a short abstract, and names and contact information of the authors. Submissions will be fully refereed by three PC members. Submissions must be made electronically (in PDF format), preferably via the Submission and Evaluation link (see above). The organizers can be reached by e-mail at: dsn2009-nanocomputing[at]laas.fr. Authors of accepted papers must guarantee that their paper will be presented at the Workshop. Accepted papers will be published in a supplement volume of the DSN 2009 proceedings. About IOLTS and DSN: In 2009, IOLTS and DSN will be held back to back in geographically close sites in Lisbon area (IOLTS finishing two days before WDSN09). IOLTS and WDSN cover technically close, though complementary, domains. This provides a unique opportunity to interested participants attending both events to benefit from a comprehensive coverage of topics related to dependable and secure computing and critical applications, spanning technology level, gate-level and RTL level issues, analysis and assessment techniques as well as architectures encompassing also software and system levels. |
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Workshop Organizers
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Program Committee
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Further InformationFor more information about DSN-2009 and the venue,
please visit the conference web site at: http://www.dsn.org. |
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| Last Update: 2010-05-15 0:25 |