WDSN08-Pgm


	2nd Workshop on Dependable and Secure Nanocomputing Friday June 27, 2008, Anchorage, AK, USA
	Organizers:	• Jean Arlat, LAAS-CNRS, Université de Toulouse, France • Cristian Constantinescu, AMD, Fort Collins, CO, USA • Ravishankar K. Iyer, UIUC, Urbana-Champaign, USA • Michael Nicolaïdis, TIMA, Université de Grenoble, France

Program and Contributions

[For a panoramic snapshot of the attentive audience during the Invited talk click here]

Schedule	Contributions (Title links to the .pdf version of written material; Presenter for multiple authorship)	Slides
09:00-10:30 SESSION 1 Opening and Defect & Failure Modes in Nanoscale Technologies	1a - Introduction and Invited Talk Moderator: Ravishankar K. Iyer
	Introduction to the Workshop Jean Arlat	0.3Mb
	Invited Talk – Sustaining Error Resilience: Case Study of the IBM POWER6™ Microprocessor Pia Sanda, IBM Systems & Technology Group, Poughkeepsie, NY, USA	1.7Mb
	1b - Defect and Fault Models in Nanoscale Technologies Moderator: Alan Wood, Sun Microsystems, Menlo Park, CA, USA
	Developing Fault Models for Nanowire Logic Circuits Daniel Gil, David de Andrés, Juan-Carlos Ruiz, Pedro Gil — Universidad Politécnica de Valencia, Spain	3.2Mb
	SER Characterization of an Advanced Network Processor using Accelerated Neutron Beam Nelson Tam(1), ShiJie Wen(2), Noam Lewis(3), Richard Wong(2), Armen Karapetov(4), Oded Rozenstein(4), Haim Boot(3), Reuven Cohen(3), Usama Nassir(1) — (1) Marvell Semiconductor, Inc., Santa Clara, CA, USA; (2) Cisco Systems, San Jose, USA; (3) Marvell Israel Ltd, Yokneam, Israel; (4) EZchip Technologies Ltd., Yokneam, Israel	0.6Mb
	Modeling Microprocessor Faults on High-Level Decision Diagrams Raimund Ubar, Jaan Raik, Artur Jutman, Maksim Jenihhin — Tallinn University of Technology, Estonia; Martin Instenberg, Heinz-Dietrich Wuttke — Ilmenau Technical University, Germany	0.3Mb
10:30-11:00	Coffee Break
11:00-12:30 SESSION 2 Performance and Security Issues in Hardware Design	2a - Asynchronous Circuits Moderator: Nithin M. Nakka, University of Illinois at Urbana-Champaign, USA
	Performance Comparison between Self-timed Circuits and Synchronous Circuits Based on the Technology Roadmap of Semiconductors Masashi Imai, Takashi Nanya — The University of Tokyo, Japan	5.1Mb
	Concurrent Fault Detection for Secure QDI Asynchronous Circuits Konrad J. Kulikowski, Mark G. Karpovsky, Alexander Taubin, Zhen Wang — Boston University, MA, USA; Adrian Kulikowski — Deloitte & Touche, New York, NY, USA	0.6Mb
	2b - Intrusion Detection Devices Moderator: Daniel J. Sorin, Duke University, Durham, NC, USA
	Quantum Wireless Intrusion Detection Mechanism Tien-Sheng Lin(1,2), I-Ming Tsai(1), Sy-Yen Kuo(1) — (1) National Taiwan University, Taipei, Taiwan; (2) Lan Yang Institute of Technology, Ilan, Taiwan	1.5Mb
	Low-Cost Self-Test of Crypto Devices Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre, LIRMM, Université de Montpellier, France	2.7Mb
	Hardware Implementation of Information Flow Signatures Derived via Program Analysis Paul Dabrowski(1), William Healey(1), Karthik Pattabiraman(1), Shelley Chen(2), Zbigniew Kalbarczyk(1), Ravishankar K. Iyer(1) — (1) University of Illinois at Urbana-Champaign, USA; (2) SAIC, Champaign IL, USA	0.2Mb
12:30-14:00	Lunch
14:00-15:30 SESSION 3 Mitigation & Resilience Techniques for Nanocomputing and Closing	3a - Fault Tolerance Techniques Moderator: Juan-Carlos Ruiz, Universidad Politécnica de Valencia, Spain
	Blocking and Non-blocking Checkpointing and Rollback Recovery for Networks-on-Chip Claudia Rusu(1), Cristian Grecu(2), Lorena Anghel(1) — (1) TIMA, Université de Grenoble, France; (2) University of British Columbia, Vancouver, Canada	0.2Mb
	No Free Lunch in Soft Error Protection? Ilia Polian(1), Sudhakar M. Reddy(2), Irith Pomeranz(3), Xun Tang(2), Bernd Becker(1) — (1) Albert-Ludwigs-University, Freiburg, Germany; (2) University of Iowa, Iowa City, USA; (3) Purdue University, West Lafayette, USA	1.2Mb
	3b - Reconfigurable Nanoscale Circuits Moderator: Cristian Constantinescu
	Fault Tolerance of the Input/Output Ports in Massively Defective Multicore Processor Chips Piotr Zajac(1,2), Jacques Henri Collet(1), Jean Arlat(1), Yves Crouzet(1) — (1) LAAS-CNRS, Université de Toulouse, France; (2) Technical University of Lodz, Poland	1.1Mb
	BISM: Built-in Self Map for Crossbar Nano-Architectures Mehdi Tahoori — Northeastern University, Boston, MA, USA	0.4Mb
	Combined Defect and Fault Tolerance for Reconfigurable Nanofabrics David de Andrés, Juan-Carlos Ruiz, Daniel Gil, Pedro Gil — Universidad Politécnica de Valencia, Spain	0.3Mb
	3c - Wrap up Moderator: Jean Arlat	0.1Mb
15:30-16:00	Adjourn — Coffee Break