Schedule
|
Contributions (Written
material is a available from IEEE Xplore (links: part1 & part2); Presenter for
|
Slides |
08:30-10:00
SESSION
1
Opening
and
Special Focus |
Moderator: Cristian
Constantinescu, AMD, Fort Collins, CO, USA |
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Introduction
to the Workshop
Jean Arlat, Cristian Constantinescu, Johan
Karlsson, Ravishankar K. Iyer, Michael Nicolaïdis |
0,4 Mb |
Massive
Statistical Process Variations: A Grand Challenge for Testing Nanoelectronic
Circuits Bernd
Becker*, Sybille Hellebrand**, Ilia
Polian***, Bernd Straube & Wolfgang
Vermeiren****, Hans-Joachim
Wunderlich*****
* University of Freiburg,
** University of Paderborn, *** University of Passau, **** Fraunhofer IIS/EAS
Dresden, ***** University of Stuttgart; Germany
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6,6 Mb |
10:00-10:30 |
Coffee
Break |
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10:30-12:00
SESSION
2
Soft
Errors
and
Intermittent Faults
|
Moderator:
Alan Wood, Oracle Corp., Menlo Park,
CA, USA |
|
Towards
Understanding the Effects of Intermittent Hardware Faults on Programs
Layali
Rashid, Karthik Pattabiraman, Sathish Gopalakrishnan, The University
of British Columbia, Canada |
1.1 Mb |
Gate
Input Reconfiguration for Combating Soft Errors in Combinational
Circuits
Warin
Sootkaneung, Kewal K. Saluja, University of Wisconsin-Madison, USA
|
1.6 Mb |
Verification
of Soft Error Detection Mechanism through Fault Injection on Hardware
Emulation Platform
Oscar Ballan*, Umberto Rossi*, Anne Wantens**, Jean-Marc
Daveau***, Salvatore Nappi****, Philippe Roche***
STMicrolectronics * Agrate Brianza, Italy, ** Grenoble, France,
*** Crolles, France, **** Arzano, Italy |
Unfortunately,
the paper could not be presented |
—> Alternative
Presentation:
Soft
Error Rate Trends
Alan Wood |
1.2 Mb |
12:00-13:30 |
Lunch |
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13:30-15:00
SESSION
3
Fault-Tolerant
Architectures
and
Resilience
|
Moderator:
Helia Naeimi, Intel Corporation, Santa Clara, CA, USA
|
|
Pair
and Swap: An Approach to Graceful Degradation for Dependable Chip
Multiprocessors
Masashi Imai, Tomohide Nagai, The University of Tokyo; Takashi
Nanya, Canon Inc., Tokyo; Japan |
2.6 Mb |
Implementation of
Self-Healing Asynchronous Circuits at the Example of a Video-Processing
Algorithm
Thomas Panhofer, Werner Friesenbichler, Andreas
Steininger, Vienna
University of Technology, Austria |
1 Mb |
Fault-Tolerant
Communication in 3D Integrated Systems
Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi, TIMA Laboratory,
Grenoble, France |
2 Mb
|
15:00-15:30 |
Coffee
Break |
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15:30-17:30
SESSION
4
Robustness
Enhancement & Trust Management
and
Closing
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Moderator:
Takashi Nanya, Canon Inc., Tokyo, Japan
|
|
Towards
Self-Timed Logic in the Time-Triggered Protocols
Markus Ferringer, Vienna University of Technology, Austria
|
3.5 Mb |
A
Concept of a Trust Management Architecture to Increase the Robustness
of Nano Age Devices
Thilo Pionteck, University of Lübeck; Werner Brockmann,
University of Osnabrück; Germany
|
1 Mb |
Workshop Wrap-Up: Johan Karlsson
Session
Moderators and All Participants!
|
53 Kb |
17:30 |
Adjourn |
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