Sunflower

IFIP Working Group 10.4
Dependable Computing and Fault Tolerance

60th Meeting

Jhong Li City, Taoyuan, Taiwan

July 1-4, 2011
Previous Page

Meeting Host
 Sy-Yen Kuo, National Taiwan Univ., TW

Program-at-a-Glance and Contents

Workshop on Hardware Issues in Dependable and Security Computing

Workshop 
Coordinators
Jean Arlat, LAAS-CNRS, FR
Zbigniew Kalbarczyk, UIUC, US
Takashi Nanya, Canon, JP
Session 0, Introduction
Session 1, Emerging Hardware Development in Taiwan
Session 2, Hardware Architectures and Systems
Session 3, Hardware-Related Fault Pathologies
Session 4, Assessment Methods and Techniques
Session 5, Workshop Wrap-Up

Business Meeting

Research Reports

List of Attendees

Workshop  on Hardware Issues in Dependable and Secure Computing 

July 2-3, 2011 (Saturday/Sunday)


Session 0, Introduction
Jean Arlat, Zbigniew Kalbarczyk, Takashi Nanya
Workshop Overview
.pdf icon 630 KB

Session 1, Emerging Hardware Development in Taiwan
Bruce Smith, IBM, TW
IBM's ODM Development Model in Taiwan
 .pdf icon 1.8 MB
Rex Sung, Pegatron, TW
Next Generation HPC Design Concept
Shih-Chieh Chang, National Tsing Hua Univ., TW
Better Life and Better Environment - National Program for Intelligent Electronics in Taiwan		 .pdf icon 2.0 MB
Yen-Kuang Chen, Intel, TW
Challenges and Opportunities for Connected Context Computing

Session 2, Hardware Architectures and Systems
Hermann Kopetz, TU-Vienna, AT
System-Level Error-Handling Mechanisms in the Time-Triggered Architecture
.pdf icon  2.1 MB
Tomohiro Yoneda, National Institute of Informatics, JP
Dependability Techniques for Networks on Chips		 .pdf icon  1.1 MB
Rakesh Kumar, UIUC, US
Stochastic Computing: Embracing Errors in Architecture and Design of Processors and Applications		 .pdf icon  1.1 MB

Session 3, Hardware-Related Fault Pathologies
Michel Renovell, LIRMM-CNRS, FR
Testing for Realistic Spot Defects in CMOS Technology: From a Deterministic to a Statistical View
.pdf icon  545 KB
Nobuyasu Kanekawa, Hitachi, JP
Fault Pathologies Caused by Moore's Law, and Remedies 		 .pdf icon  905 KB
Subhasish Mitra, Stanford, US
Robust Systems for Scaled CMOS and Beyond		 .pdf icon  3.8 MB
Alan Wood, Oracle, US
System Level Issues due to Technology Trends		 .pdf icon  1.4 MB

Session 4, Assessment Methods and Techniques
Ravi Iyer, UIUC, US
New Generation Hardware Support for Reliability and Security of Systems 		.pdf icon  815 KB
Johan Karlsson, Chalmers Univ., SE
Fault Injection-Based Assessment of Software Mechanisms for Hardware Fault Tolerance		 .pdf icon  299 KB
Chin-Long Wei, National Central Univ., TW
Design for Stressability of Analog CMOS Circuits for Gate-Oxide Reliability Enhancement

Session 5, Workshop Wrapup
Wrapup Reports
.pdf icon  410 KB


 

Business Meeting

Rick Schlichting, AT&T Labs, US
Overall Presentation and News
 .pdf icon  7.0 MB

 

Research Reports

July 4, 2011 (Monday)

Yennun Huang, Academia Sinica, TW
Digital Convergence in Taiwan: Challenges and Opportunities
 .pdf icon  598 KB
Karthik Pattabiraman, Univ. of British Columbia, CA
Backtrack: Diagnosing Hardware Faults using Software Techniques
 .pdf icon  1.3 MB
Aad van Moorsel, Newcastle Univ, UK
User-Managed Access Control for Web 2.0 Applications
 .pdf icon  1.7 MB
Nobuyasu Kanekawa, Hitachi, JP
My Recent Events and Activity on IEC 61508
 .pdf icon  168 KB
Masashi Imai, Univ of Tokyo, JP
Duplicated Execution Method for NoC-Based Multiple Processor Systems with Restricted Private Memories
 .pdf icon  807 KB

List of Attendees

Names and Contact Information
.pdf icon  37 KB