June 27, 2011
Nanocomputing and related enabling technologies hold
the promise of higher performance and lower power consumption, as well
as increased communication capability and functionality. In addition
to the impact on today computerized systems, such a trend
is an essential lever to foster the emerging cyberphysical system paradigm.
However, the dependability and security of these unprecedentedly small
devices, of their deployment, and of their interconnection remains uncertain.
The main sources of concern are:
- Nanometer devices are expected to be highly
sensitive to process variations. The guard-bands used
today for avoiding the impact of such variations will not represent
a feasible solution in the future. As a consequence, timing errors
and their higher frequency of occurrence have to be addressed.
- New and intricate failure modes,
specific to nanoscale dimensions and new materials, are expected
to raise serious challenges to the design and test engineers.
- Environment induced errors, such
as single event upsets (SEU) or single event transients (SET), are
likely to occur more frequently than in the case of conventional semiconductor
- Design of hardware architectures encompassing
resilience techniques are needed to
achieve the development of reliable and highly energy efficient systems.
- The increased complexity of the systems based
on nanotechnology will require improved computer aided design (CAD) tools, as well as
better validation techniques.
- The security of nanocomputing systems may
be threatened by malicious attacks targeting new vulnerable
areas in the hardware.
Hardware implemented fault tolerance features (encompassing
codes, as well as space and time redundancy) will be increasingly employed
for dealing with these dependability issues. Providing high dependability
to the end users will require improved error reporting, recovery, and
system manageability. As a consequence the role of software solutions
will increase as well. Software will also play the leading role in the
improvement of design and validation tools. Furthermore, improved parallel
processing programming paradigms are needed due to the advent of multicore
processor and Network-on-Chip architectures.
The previous four editions
of the Workshop — held from DSN-2007 to DSN-2010 — have
increasingly attracted the attention of the DSN audience to the importance
of hardware-related issues. Indeed, DSN is the appropriate forum for
discussing these challenges and potential solutions.
Accordingly, building on the success of these previous
editions, we would like to continue to focus the Workshop on Designing,
Manufacturing, and Assessing Dependable Nanocomputing Systems, with a
special attention being paid, for this year's edition, to the following
- Nanocomputing architectures for high dependability
- Design, validation,
and manufacturing techniques for coping with increased complexity
- Dependability of application-specific nanocomputing
architectures, including SoCs-NoCs
- Failure modes and testing issues specific
Contributions related to these main topics will allow
the Workshop to continue the debate on the increasingly developing issues
posed by nanocomputing, as well as the best solutions for providing highly
dependable and secure systems and networks to the end-users. In that
respect, potential topics of interest include, but are not limited to:
failure modes and risk assessment, yield and mitigation techniques in
nanoscale technologies, vulnerability analysis of hardware devices and
design of countermeasures for secure operation, on-line adaptive and
reconfigurable nanoarchitectures, design techniques for developing resilient
nanosystems, fault-tolerant architectures specific to nanoscale circuits,
scalable verification and testing methodologies, network on chip and
communication protocols, etc.
Submission and Selection Process
is open to all researchers, system developers and users, from
both industry and academia, who are involved with or have an
interest in dependability and security of hardware technologies for
nanocomputing. Both invited and submitted contributions will be included
in the Workshop program.
All prospective contributors should submit
an extended abstract, work-in-progress report or position paper. Submissions
must be original work with no substantial overlap with previously published
papers or simultaneous submissions to a journal or conference with proceedings.
The submissions should conform to the IEEE Computer Society camera-ready 8.5"x11" two-column
camera-ready format (IEEE
and should not exceed six pages (including all text, figures, references, and
appendices). They should explain the contribution to the field and the novelty
of the work, making clear the current status of the work. Each submission should
start with a title, names and contact information of the authors, as well as
a short abstract. Submissions
will be fully refereed by three PC members. Authors of accepted
papers must guarantee that their paper will be presented at the Workshop.
Accepted papers will be published in a Workshops only "DSN-W" volume
of the DSN-2011 Proceedings and archived on IEEE Xplore.
must be made electronically, as a single Portable Document Format (PDF)
file, via the Submission
and Evaluation link (see top of page). We recommend that you embed fonts
whenever possible to improve portability. We also strongly recommend you
print the file and review it for integrity (fonts, symbols, equations,
etc.) before submitting it. A defective printing of your paper can
undermine its chance of success.The organizers can
be reached by e-mail at: dsn2011-nanocomputing[at]laas.fr.
deadline [delayed]: March
notification [delayed]: April 20, 2011
ready copy : May 1, 2011
- Jean Arlat, LAAS-CNRS, Toulouse, France — Email: jean.arlat[at]laas.fr
- Cristian Constantinescu, AMD, Fort Collins, CO,
— Email: cristian.constantinescu[at]amd.com
- Johan Karlsson, Chalmers University of Technology,
Göteborg, Sweden — Email: johan[at]chalmers.se
- Takashi Nanya, Canon Inc., Tokyo, Japan —
- Alan Wood, Oracle, Redwood City, CA, USA — Email: alan.wood[at]oracle.com
- Davide Appello, STMicroelectronics, Agrate Brianza, Italy
- Vikas Chandra, ARM R&D, San Jose, CA, USA
- Yves Crouzet, LAAS-CNRS, Toulouse, France
- David de Andrés, Technical University of Valencia, Spain
- Eishi Ibe, Hitachi Ltd, Yokohama, Japan
- Ravishankar K. Iyer, University of Illinois, Urbana-Champaign, USA
- Jian-Hui Jiang, Tongji University, Shanghai, China
- Sy-Yen Kuo, National Taiwan University, Taipei, Taiwan
- Erik Larsson, Linköping University, Sweden
- Helia Naeimi, Intel Corporation, Santa Clara, CA, USA
- Michael Nicolaïdis, TIMA, Grenoble, France
- Toshinobu Ono, Renesas Electronics, Kanagawa, Japan
- Rubin A. Parekhji, Texas Instruments, Bangalore, India
- Sung-Bum Park, MagnaChip Semiconductor, Seoul, Korea
- Karthik Pattabiraman, University of British Columbia, Vancouver, Canada
- Andreas Steininger, Vienna University of Technology, Austria
- Cheng-Wen Wu, National Tsing Hua University, Hsinchu, Taiwan
- Hans-Joaquim Wunderlich, University of Stuttgart, Germany
- Qiang Xu, The Chinese University of Hong Kong, Hong Kong, China
- Tomohiro Yoneda, National Institute of Informatics, Tokyo, Japan
For more information about DSN-2011 and the venue,
please visit the conference web site at: http://www.dsn.org.
For workshop information, please send an email to the workshop organizers
Information about the previous editions of the Workshop are available
at: http://www.laas.fr/WDSN07, http://www.laas.fr/WDSN08, http://www.laas.fr/WDS09 and http://www.laas.fr/WDSN10